1. Field of the Invention
The present invention relates to semiconductor devices and more particularly, to improved methods of forming bond pads using dual damascene.
2. Description of the Related Art
Semiconductor manufacturers must continually improve the power and performance of semiconductor devices while keeping the device size to a minimum. In an effort to maintain a small device size, most semiconductor manufacturers reduce individual components of the device to minimal dimensions. Further, manufacturers are vertically integrating more and more of these components, as opposed to using only horizontal integration, to reduce the device area consumed by the components. Vertical integration is typically achieved by using several conductive layers in the device and interconnecting these layers using, for example, inter-level contacts known in the art as vias or via interconnects.
As individual component dimensions become smaller, it becomes more difficult to interconnect the various conductive layers. A recent approach to solving the problem of interconnecting the various conductive layers involves etch and mask sequences generally known in the art as damascene techniques. The damascene technique involves forming a plurality of trenches in a layer of insulator and subsequently filling them with metal which is then polished down to the surface of the insulator to form the desired metal pattern. In a process generally known as dual damascening, both the metal trenches as described above and the via interconnects electrically connecting the aforementioned metal pattern and various other conductive layers are typically filled substantially simultaneously.
In the conventional dual damascene technique, via interconnects are typically formed substantially simultaneously with the overlying metallization which includes bond pads. This technique requires that the holes through the insulator (the holes will eventually be filled with metal or other conductive material to form the via) be formed prior to the deposition of the layer of photoresist used in the subsequent metallization lithography. Bond pads formed of the overlying metallization are suitably located on the upper surface of the semiconductor integrated circuit. The bond pads are used to electrically connect external circuitry to the underlying metallization layer. Typically, bond wires formed of metallic conductors such as, for example, Al, Cu, and/or alloys thereof are used to connect the bond pads to external leads capable of connection to the external circuitry. In some cases, an integrated package referred to as a flip chip package can be used. The flip chip package generally has very short, or, in some cases no bond wires.
FIG. 1A represents a cross sectional view of a stacked semiconductor structure 100. The stacked semiconductor structure 100 includes a semiconductor substrate 102, an underlying conductive layer 104 overlaid with a layer of insulator 106. A plurality of via holes 108 form a conduit between the underlying conductive layer 104 and a bond pad trench 110. The bond pad trench 110 is formed by removing a portion of the layer of insulator 106 to a depth AT@ approximating the desired thickness of the bond pad to be formed.
After the via holes 108 and the bond pad trench 110 have been formed, the metallization layer 112 is placed upon the insulator layer 106 substantially simultaneously filling the via holes 108 and the bond pad trench 110 using a blanket deposition process. The metallization layer 112 typically extends above the upper surface of the insulator layer 106 to a predetermined height. In order to form a bond pad, a portion 112-1 of the metallization layer 112 extending above the upper surface of the insulator layer 106 must be removed so as to expose the insulator layer 106. In this manner, a bond pad is formed of the metal remaining within the bond pad trench 110.
FIG. 1B is an cross sectional view a bond pad 114 formed by removing the portion 112-1 of the metallization layer 112. The portion 112-1 is removed in a process referred to as polishing. Polishing removes the portion 112-1 by, for example, physically abrading the metal included in the portion 112-1. One such method of abrading the metal included in the portion 112-1 includes using a combination of a rotating pad, or other mechanical device, accompanied by a chemical etch, or slurry. The rotating polisher pad typically removes the portion 112-1 of the by a combination of physical abrasion caused by the mechanical action of the polisher and the slurry.
Unfortunately, the rotating polisher pad must be subject to a force applied perpendicular to the insulator layer 106 in order to properly remove the portion 112-1. This force causes the rotating polisher pad to flex thereby forming a convex polishing surface. The flexing in the rotating polisher pad results in partial removal of the metal deposited within the bond pad trench 110. The removal of the metal deposited in the bond pad trench 110 due to the convex shape of the polisher pad in combination with the chemical etch action of the slurry results in a substantial reduction in the bond pad thickness from the thickness T to a thickness T. In some cases the thickness T is of such a magnitude as to expose the insulator 106.
The reduction of bond bad thickness can result in exposing a portion 106-1 of the insulator layer 106. The exposure of the insulator 106 results in poor mechanical and electrical contact with a subsequently attached bond wire. In some cases, the presence of exposed insulator layer 106 can result in the formation of voids 120 between the bond pad 114 and the bond wire 150 as illustrated in FIG. 1C. The presence of voids 120 can result in high current densities through the unvoided portions of the bond pad/bond wire junction. The high current densities may result in electromigration of the metal included in the bond pad. Electromigration of the bond pad metal may result in long term unacceptable Failure In Time (FIT) rates.
Thus there is a need for dual damascene techniques which eliminate the possibility of forming bond pads having regions of thin metallization. The dual damascene technique should also prevent the formation regions of exposed insulator thereby increasing the probability of poor electrical contact with subsequently placed bond wires.